Concatenated turbo product codes for high performance satellite and terrestrial communications

ABSTRACT

Architecture for enhancing the encoding/decoding of information of a channel. A stream of incoming information bits are arranged into a first array of information bits. The first array of information bits are processed into a first code of bits, which bits form a plurality of first code words having a minimum distance to neighboring error events. Selected bits of the first code are rearranged into a second array of bits by intermittent successive rotations of the selected bits of the first code. A second code is then generated from the second array of bits to increase the minimum distance to the neighboring error events.

[0001] This application claims priority under 35 U.S.C. §119(e) fromU.S. Provisional Patent application Serial No. 60/279,180 entitled“Concatenated Turbo Product Codes for High Performance Satellite andTerrestrial Communications” and filed Mar. 27, 2001.

BACKGROUND OF THE INVENTION

[0002] 1. Technical Field of the Invention

[0003] This invention is related to turbo codes, and more specifically,architecture for iterative processing of a channel of information usinga second concatenated turbo code generated from a first turbo code.

[0004] 2. Description of the Related Art

[0005] Digital communications links are used for the efficient andflexible transmission of a wide range of data services. In general, asthese services and their supporting networks migrate towards higherrates, and more bursty packet oriented structures, it is important thatthe physical layer have both access techniques and modulation/codingtechniques to efficiently convey this type of data. This is especiallyimportant in many applications in which both bandwidth and power arelimited resources. Many industry forums and regulatory bodies haveconcluded that technology advances in power and spectrum efficiency areneeded to support the projected use of these services.

[0006] It is widely accepted that Forward Error Correction (FEC) is avaluable technique to increase power and spectrum efficiency, and thuswill have an important role in these systems. However, the developmentof FEC with increased coding gain and decreased overhead does have alimit. This limit arises from Shannon's Channel Capacity theorem(published in a 1948 paper entitled “A Mathematical Theory ofCommunication”) that states that the Bit Error Rate (BER) performance ofany rate code will be bounded. This bound is illustrated in FIG. 1, andshows that the maximum coding performance that can be achieved on theantipodal channel for a variety of code rates, e.g., ¼, ⅓, ½, ⅔, and ⅘.No codes can perform better than this theoretical maximum. This alsoholds for any concatenation of codes.

[0007] The task of the code designer then is to develop a codec (anencoder and decoder pair) that exhibits a performance curve that is asclose as possible to Shannon's theoretical maximum. However, anotherimplication of the capacity theorem is that the closer the code is tothe theoretical maximum, the more complex it will to become toimplement.

[0008] What is needed is an algorithm that encodes/decodes informationbits in a way that approaches the theoretical channel capacity, but isstill practical to implement.

SUMMARY OF THE INVENTION

[0009] The present invention disclosed and claimed herein, in one aspectthereof, comprises architecture for enhancing encoding/decodinginformation of a channel. A stream of incoming information bits arearranged into a first array of information bits. The first array ofinformation bits are processed into a first code of bits, which bitsform a plurality of first code words having a minimum distance toneighboring error events. Selected bits of the first code are rearrangedinto a second array of bits by intermittent successive rotations of theselected bits of the first code. A second code is then generated fromthe second array of bits to increase the minimum distance to theneighboring error events.

[0010] In another aspect thereof, the stream of incoming informationbits into a first array of information bits, wherein the first array ofinformation bits is processed into a first TPC of bits, which first TPCincludes a first set of column parity bits and a first set of row paritybits. The first array of information bits of the first code is thenarranged into a second array of bits in a pseudo-random manner, and fromwhich a second set of column parity bits and a second set of row paritybits are generated from the second array of bits. The first TPC, thesecond set of column parity bits, and the second set of row parity bitsare then transmitted.

[0011] In still another aspect thereof, the stream of incominginformation bits are arranged into a first array of k-by-k informationbits. The first array of information bits are then processed into afirst code of bits, which first code of bits form an (n+1,k)² TPC ofExtended Hamming code words, and which first code has k columns thatinclude the information bits. Selected bits of the first code are thenrearranged into a second array of bits by rotating the k columns of thefirst code in a successively increasing manner. A second code is thengenerated from the second array of bits by encoding the k leftmost bitsof each horizontal code word with a (k+1,k) parity code word.

[0012] In yet another aspect thereof, the stream of incoming informationbits into a first array of information bits, which first array ofinformation bits are then processed into a first code of bits, whichfirst code of bits form an (n+1,k)² TPC of Extended Hamming code words,and which first code has k columns that include the information bits.Selected bits of the first code are then rearranged into a second arrayof bits by rotating n columns of the first code in a successivelyincreasing manner. A second code is then generated from the second arrayof bits by encoding the k leftmost bits of each horizontal code wordwith a (n+1,n) parity code word.

[0013] In yet still another aspect thereof, the stream of incominginformation bits into a first array of information bits, which firstarray of information bits is then processed into a first code of bits,the first code of bits forming a (k+1,k)² TPC of row elements and columnelements. The first code is rearranged into a second array of bits suchthat the row elements and the column elements fall along correspondingdiagonals. Encoding the second array of bits then generates a secondcode.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] For a more complete understanding of the present invention andthe advantages thereof, reference is now made to the followingdescription taken in conjunction with the accompanying Drawings inwhich:

[0015]FIG. 1 illustrates a graph of the theoretical limits defined byShannon's Channel Capacity Theorem on several conventional code rates;

[0016]FIG. 2 illustrates a block diagram of a 2-dimensional TPC decoder,according to a disclosed embodiment;

[0017]FIG. 3 illustrates the general process for developing a C-TPCutilizing Extended Hamming codes, according to a disclosed embodiment;

[0018]FIG. 4 illustrates a general layout of a concatenated (16,11)Extended Hamming code;

[0019]FIG. 5 illustrates the (16,11)² C-TPC of FIG. 4, showing theinformation bits being rotated;

[0020]FIG. 6 illustrates a general circuit block diagram for an encoderfor generating a (4544,3249) C-TPC from a (64,57) Extended Hamming TPC,according to a disclosed embodiment;

[0021]FIG. 7 illustrates a graph of simulated performance curves of therespective concatenated (336,121) TPC (C-TPC1) and the (256,121)“parent” TPC;

[0022]FIG. 8 and FIG. 9 illustrate a comparison of the relative size andstructure of the (16,11) concatenated C-TPC1 and the (64,57)concatenated C-TPC2;

[0023]FIG. 10 illustrates a graph of the simulated performance curvesfor C-TPC2 900, and in comparison with the performance curve of the“parent” (64,57)² TPC;

[0024]FIG. 11 illustrates a four-dimensional code embodiment achieved byadding an additional set of parity bits to the C-TPC2 of FIG. 9;

[0025]FIG. 12 illustrates a graph of the performance curve results forthe code of FIG. 11;

[0026]FIG. 13 illustrates a graph of the simulated performance resultsfor C-TPC3 utilizing a staggered rotations interleaver;

[0027]FIG. 14 illustrates the code C-TPC2 of FIG. 9 where an additionala parity bit is added;

[0028]FIG. 15 illustrates a graph of the simulated performance curvesfor C-TPC4 and C-TPC5 utilizing various weighting coefficients;

[0029]FIG. 16 illustrates a variation C-TPC8 of the C-TPC5 code that isconsidered whereby both diagonals are protected via parity codes;

[0030]FIG. 17 illustrates a simple indexing scheme of an 11×11 arrayrepresenting the elements of the (11,10)² TPC;

[0031]FIG. 18 illustrates a diagonal mapping of the elements of thearray of FIG. 17 such that row and column elements fall along a firstdiagonal and a second diagonal, beginning the indexing at a center cellof the array and, working downward and to the right;

[0032]FIG. 19 illustrates a graph of simulated performance curvesassociated with the code of FIG. 16; and

[0033]FIG. 20 illustrates a graph of simulated performance curves of aC-TPC9 (64,57)² code with various weighting coefficients.

DETAILED DESCRIPTION OF THE INVENTION

[0034] The disclosed architecture provides a class of codes that offerperformance closer to Shannon's limit than the traditional concatenatedcodes. These codes, called Turbo Product Codes (TPCs), are the iterativesoft decision decoding of a product code. TPCs are a class of codes witha wide range of flexibility in terms of performance, complexity, andcode rate. This flexibility allows TPCs to be used in a wide range ofapplications. For example, one TPC considered exhibits a code rate of ⅘and a coding gain of 7.4 dB at a bit error rate (BER) of 10⁻⁶.

[0035] The disclosed Concatenated Turbo Product Codes (C-TPCs) are builtfrom existing TPCs, and enable an increase in a minimum distance thatenables significantly improved performance in lower code rates. Thefollowing innovations when combined, enable the design of a wide rangeof C-TPCs that provide high performance while emphasizing low complexityto enable low-cost and high-speed implementations.

[0036] Referring now to FIG. 2, there is illustrated a basic blockdiagram of a two-dimensional TPC decoder 200. The decoder 200 istwo-dimensional in that data is processed in horizontal and verticaldirections, and in this particular embodiment, utilizing Cyclic-2 PMLSISO (Pseudo Maximum Likelihood Soft-Input Soft-Output) decoders.

[0037] In 1994, the applicant of this invention invented a new softdecision block decoding technique called Pseudo Maximum Likelihooddecoding and its cyclic variations (in particular, the one calledCyclic-2 PML) that performs to within a few tenths of a dB (decibel) ofmaximum likelihood decoding, but with significantly reduced complexity.For many useful codes, this technique results in the most efficientdeterministic decoders known. The details of this algorithm werepublished in the following proceedings, “PRAGMATIC APPROACH TOSOFT-DECISION DECODING OF LINEAR BLOCK CODES” by Thesling, W. H., IEEProceedings on Communications 1995, the entirety of which is herebyincorporated by reference. A modification of the PML algorithm wassubsequently developed to provide Soft-Output information resulting in aSISO decoder. The modification includes the development of a soft-outputlikelihood metric that is easily computed with the information readilyavailable from the Cyclic-2 (C2) PML algorithm. The SISO C2-PMLalgorithm is disclosed in detail in U.S. Pat. No. 5,930,272 entitled“BLOCK DECODING WITH SOFT OUTPUT INFORMATION” by William H. Thesling,filed Jun. 10, 1997, and issued July 27, 1999, the entirety of which ishereby incorporated by reference.

[0038] Referring again to FIG. 2, a first channel data input 202 to thedecoder 200 accommodates channel data, and a second feedback input 204accommodates feedback information. A selector circuit 206 moves betweenthe first channel data input 202 and the second feedback input 204 toselect the corresponding data for input to a first Cyclic-2 PML decoder208. The first cyclic decoder 208 processes the rows (or horizontalbits) of the input code blocks, and passes decoded information therefromto a first normalization-and-weighting-coefficient function (NWC) block210 (also denoted NWC1) via a NWC1 input 212. The NWC1 block 210performs the function of normalizing the received decoded data, and alsodeveloping a weighting coefficient for the code words. In order toperform this function, the NWC1 block 210 has a NWC1 raw data input 214that connects to the first channel data input 202 to receive the rawchannel data provided thereto.

[0039] The resultant data of the NWC1 block 210 is passed to a secondCyclic-2 PML SISO decoder 216 via a second decoder input 218, whichsecond cyclic decoder 216 performs decoding of the columns (or verticalbits). The second decoder 216 also has a second raw data input 220 thatconnects to the first channel data input 202 to receive the raw channeldata provided thereto.

[0040] The processed information of the second cyclic decoder 216 ispassed to a second NWC block 222 (also denoted hereinafter as NWC2) viaa NWC2 input 224 for performing normalization of the received decodeddata, and also for developing a weighting coefficient for the codewords. In order to perform this function, the NWC2 block 222 has a NWC2raw data input 226 that connects to the first channel data input 202 toreceive the raw channel data provided thereto. The output of the NWC2block is output to decoded data output 228 for subsequent processing(not shown), and also fed back to the first cyclic decoder 208 via thefeedback input 204. The feedback input 204 facilitates iterativeprocessing of the data utilizing the decoder 200.

[0041] The performance of TPCs is quite good for the higher rate codes(rate ⅘^(th) and above) achieving performance approximately 1.2 B awayfrom the Shannon' theoretical limit for a 4K block TPC at BER=10⁻⁶. Atlower BERs, the performance curves show a “flare.” For example, the(64,57)² TPC achieves BER=10⁻⁶ performance at Eb/No=3.2 dB. However, toachieve a BER of 10−10 , an Eb/No of 4.2 dB is required. Forapplications requiring quasi error-free performance, the additionalEb/No required is significant.

[0042] To further increase the performance of TPCs in the lower BERrealm, an enhancement is applied to TPCs that, in some ways, is similarto the concatenation of convolutional codes, but is constructed fromExtended Hamming codes, and can be decoded with an efficient SISOdecoding algorithm.

[0043] Referring now to FIG. 3, there is illustrated the general process300 for developing a C-TPC utilizing Extended Hamming codes, accordingto a disclosed embodiment. The (n+1,k)² TPC of Extended Hamming codewords has n+1 columns, of which k columns include the information bitsand parity bits and, and n+1-k columns include only parity bits.Similarly, the (n+1,k)² TPC has n+1 rows, of which k rows include theinformation bits and parity bits and, and n+1-k rows include only paritybits.

[0044] Generally, the idea behind concatenated codes is to apply extracodes that are capable of identifying errors of the “parent” TPC. Theencoding process 300 for generating a concatenated code begins with achannel of data comprising a stream of information bits 302. The streamof information bits 302 is formatted into a square matrix (ortwo-dimensional array) 304 of X- by- X information bits. The array 304is then encoded top-to-bottom, and column by column, to derive paritybits for each column, which encoding process appends the set ofcorresponding column parity bits (PBs) 306 to the array 304. The nextstep is to then perform left-to-right row encoding on the array 304 andthe recently derived column PBs 306, resulting in a set of row PBs 308that include a set of parity bits for each row, and that are appended tothe array 304 of information bits, and a corresponding set of row PBs310 for the column PBs 306 (also denoted hereinafter as C/R PBs). Thus afirst constituent code TPC1 is now defined by the array 304 ofinformation bits, column PBs 306, row PBs 308, and C/RPBs 310. Note thatthe first code TPC1 is in the form of an Extended Hamming code where therow PBs 308 include one extra parity bit, which is the overall parity ofrow information bits and corresponding parity bits that define the codeword for that row. Similarly, the column PBs 308 include one overallparity bit for each column of information bits and corresponding columnparity bits that define the code word for that column.

[0045] The next step is to rearrange the array 304 of information bitsand corresponding column PBs 306 by cyclically rotating columns 312 ofinformation bits (only those columns that contain both information bits304 and column PBs 306) in a successively increasing manner from left toright with an intermittent extra rotation for every R^(th) column, whereR is defined as the number of parity bits n-k in the Hamming code of(n,k) bits. That is to say that the bits of the first column are eachshifted down one bit position, with the lowest bit wrapping around tothe top position. The bits of the second column are each shifted downtwo bit positions, with the two lowest bits wrapping around to the topof the column in the array. Thus when the R^(th) column is processed,the bits of the R^(th) column are each shifted down R+1 positions withthe bits wrapping around to fill the top positions of that column. Notethat Hamming codes are cyclic, whereas Extended Hamming codes (codesthat add one extra overall parity bit) are not. Thus when using ExtendedHamming codes, column rotation is determined according to the Hammingcode parameters. For example, in a (16,11) Extending Hamming code, thenumber of columns to rotate is based upon the (15,11) Hamming code,resulting in n−k=15−11=4 as R. Every 4^(th) column will then have anextra bit rotation, except for the leftmost information bit column 314.After the column rotation is complete, there exists an X by X rotatedmatrix 316 of rotated information bits. The rotated matrix 316 includesX columns of code words.

[0046] The next step is to create a second code (or left) TPC2 byencoding all of the rows 318 of rotated (or rearranged) information bits316 and column PBs 306 (not the row PBs 308) from right to left togenerate corresponding row PBs 320, and C/R PBs 322. The second (orleft) constituent TPC2 is then defined by the rotated information bits316, the left row PBs 320, the lower column PBs 306, and the lower leftC/R PBs 322.

[0047] Referring now to FIG. 4, there is illustrated a general layout ofa concatenated (16,11) Extended Hamming code 400. The rightmost sixteencolumns form the first constituent (16,11)² code TPC1. Processing beginsby downward encoding the columns of information bits (denoted as capital“I”) to derive the corresponding column parity bits (denoted as capital“P_(V)”) Next, processing the array of information bits andcorresponding column PBs in a left-to-right fashion generates the fiverightmost columns of parity bits for the first code TPC1 (denoted as“P_(H)” for the rows of information bits, and “P_(VH)” for the rows ofencoded column parity bits “P_(V)”). The five leftmost columns of paritybits for the second code TPC2 (denoted as “P_(H2)” for the rows ofencoded information bits, and “P_(VH2)” for the rows of encoded columnparity bits “P_(V)”) are generated in a manner similar to the fiverightmost columns, in the first TPC1, except the code words (defined bythe row information bits “I” and corresponding row parity bits “P_(H2)”are constructed in a right-to-left fashion. Therefore, each column ofthe twenty-one columns, in this particular embodiment, is a code word,and each row of the sixteen rows corresponds to two code words-the firstcode word involves the leftmost sixteen bits (i.e., five parity bits“P_(H2)” and eleven information bits “I”, and the second code wordinvolves the rightmost sixteen bits (i.e., the same eleven informationbits “I” and five parity bits “P_(H)”).

[0048] This concatenated code (i.e., the first code and the second code)can easily be decoded via an iterative decoding process. The code is nowa (336,121) C-TPC with a rate=0.360. Note that the minimum distance ofthis code remains at sixteen. This suggests that the performance isworse then a (256,121) TPC by the rate difference (0.360 vs. 0.473, or1.18 dB worse). (The associated performance curves are providedhereinbelow in FIG. 7.) However, the number of nearest neighbors (thenumber of possible weight sixteen error events) is drastically reduced.For the regular (16,11)² TPC1, when a weight sixteen error event occurs,the decoder must find four rows (code words) each with four bit errors.These four bit errors must be the same in the four positions in all fourrows to assure four columns (code words) have four bit errors as well. Anovel feature of the C-TPC is that the error pattern (which is itself acode word) of these four rows must also be an error pattern when the rowis taken backwards, utilizing only the center eleven columns and theleftmost five parity bits.

[0049] For the (16,11) code, there are 1,240 weight-four code words.Thus there are 1,240²=1,537,600 possible weight-16 error events for the(16,11)² TPC. For the (16,11) code, there are only five weight-4 codewords that are also code words when taken backwards. Thus there are5×1,240=6,200 possible weight-16 error events for this (336,121) C-TPC.However, this reduction in the number of nearest neighbor code words isinsufficient to overcome the 1.18 dB of rate loss.

[0050] To further reduce the number of weight-16 error events,techniques reminiscent of the interleaver designs in TCCs (TurboConvolutional Codes) are utilized. Here, a pseudo-random interleaverbetween the right constituent TPC1 (the sixteen rightmost columns) andthe left constituent TPC2 (the sixteen leftmost columns) is used. As anexample, consider the fact that the (15,11) Hamming code is a cycliccode. Therefore, the columns can be cyclically rotated (as per the(15,11) code) in any number of positions and still have a code word.Consequently, one can construct the second (left) TPC2, by “randomly”rotating the first eleven columns of the right constituent TPC1.

[0051] Consider a simple “random” rotation scheme where each successivecolumn is rotated one more bit position then the previous column. Thisreduces the number of weight-16 code words to 5×5 (or 25). Only thoseweight-16 code words from the (16,11)² TPC1 which are completely asquare symmetric, result in code words, as per the left C-TPC. Allweight-16 code words can be eliminated if the columns are double rotatedevery 4^(th) column, which is depicted hereinbelow in FIG. 5. This arrayis only the left constituent TPC. The right constituent TPC isunchanged.

[0052] Referring now to FIG. 5, there is illustrated the (16,11)² C-TPC500 of FIG. 4, showing the information bits being rotated. Encodingbegins with one hundred twenty-one information bits arranged in an 11×11array, as illustrated in FIG. 4. First, the columns containing theinformation bits are downward encoded to derive the corresponding columnparity bits “P_(V)”, followed by the rows, to arrive at the standard (orright) TPC1 of FIG. 4. Then ten information bit columns 502 of theeleven are rotated in a successively increasing manner (from top tobottom) with an extra rotation every 4^(th) column (as depicted in FIG.4). Note that the last (or leftmost) column 504 does not partake in thisrotation operation, since only the Hamming code portion 502 is cyclic.After the “random” rotation is complete, there exist eleven column codewords. Sixteen row code words are then generated in a right-to-leftfashion to arrive at the left constituent TPC2.

[0053] Referring now to FIG. 6, there is illustrated a general circuitblock diagram for an encoder 600 for generating a (4544,3249) C-TPC froma (64,57) Extended Hamming TPC, according to a disclosed embodiment. Theencoder 600 includes an input means 602 for receiving digitalinformation that is to be encoded. The input 602 connects to a sampler604 that samples a predetermined number of information bits needed tocomplete the particular information bit matrix, i.e., 57×57=3249 bits,and formats the 3249 information bits into a square array. The array of3249 bits is then processed by columns into a (64,57) Extended HammingCode by a TPC processing block 606. As indicated hereinabove, thisprocess includes column encoding to append seven rows of column PBs tothe lower bits of the matrix, for the (64,57) TPC, as generallyrepresented in FIG. 3 by the array 304 of information bits and thecorresponding column PBs 306.

[0054] After the (64,57) Extended Hamming code is constructed by theprocessing block 606, the C-TPC needs to be constructed by completingrow encoding. Thus data flow is to a first buffer 608 where theinformation bit columns and the corresponding column PBs 306 are readthereinto from the processing block 606. The contents of the firstbuffer 608 are then transmitted out to a second processing block 612where row encoding occurs in a left-to-right manner such that the rowsof the array 304 of information bits and corresponding column PBs 306are utilized to arrive at the row PBs 308 and the C/R PBs 310. Thisprocessing step of the second processing block 612 culminates withdefining the first constituent TPC1, as illustrated in FIG. 3.

[0055] The contents of the first buffer 608 are also passed to a secondbuffer 610 for “randomizing” of the information bits. The second buffer610 receives the contents of the first buffer 608 by row, including boththe array 304 of information bits, column PBs 306, row PBs 308, and C/RPBs 310. The array 304 of information bits and corresponding column PBsare then cyclically rotated by column utilizing a “staggered diagonalrotation” rotator according to the number of check bits, i.e., seven,such that each column (except the leftmost, since only the (63,57)Hamming code is cyclic), beginning with the second leftmost column, issuccessively rotated one bit position, except that every seventh columnis rotated at least two bit positions.

[0056] The randomized contents of the second buffer 610 are then passedto a third processing block 614 where processing of the contents of thesecond buffer 610 continues with right-to-left encoding to arrive at theparity bits that will be used for the second constituent TPC2, i.e.,both row PBs 320 and C/R PBs 322. The output of the third processingblock 614 comprises both the row PBs 320 and C/R PBs 322, which are thenfed to a multiplexer 616. The multiplexer 616 then multiplexes thecontents of the second processing block 612 (i.e., TPC1) with both therow PBs 320 and C/R PBs 322 to output the concatenated code TPC2information to a communication channel 618.

[0057] Note that bit “randomizing” can occur in a variety of ways. Forexample, the disclosed architecture includes, but is not limited to, thefollowing randomizing techniques: performing right-to-left columnrotation; rotation from both top-to-bottom, and bottom-to-top; androtation indexing where each column is rotated an equal number of bitplaces N, however, the column associated with the number of parity checkbits is rotated any number bit places except N.

[0058] The C-TPC has within it both serial and parallel codeconcatenation. Finding a “good” interleaver is made much simpler inaccordance with the C-TPC due to the inherent structure of the codes,but is more difficult to solve in turbo convolutional codes.

[0059] Referring now to FIG. 7, there is illustrated a graph 700 ofsimulated performance curves (702 and 704) of the respectiveconcatenated (336,121) TPC (C-TPC1) and the (256,121) “parent” TPC. Theperformance curve 704 of the parent TPC was derived utilizing sixty-fouraxis iterations (rate=0.473) while the performance curve 702 for theconcatenated code C-TPC1 was derived utilizing sixty-four axisiterations (rate=0.360).

[0060] Note that the structure of the concatenated code C-TPC 500depicted hereinabove in FIG. 5 increases the minimum distance fromsixteen to twenty-four, thereby increasing the asymptotic coding gain(ACG) (with respect to the channel) by 1.76 dB. For the (336,121)Extended Hamming code, this represents an increase in ACG by a predictedvalue of 0.58 dB, when corrected for the rate loss. Notice that the ACGdifference at BER=10 ⁻⁸ exceeds the predicted value of 0.58 dB. This isdue to the fact that the C-TPC1 code has fewer nearest neighbors, orfewer ways a 24-bit error even can occur then the (256,121) parent codehas ways for a 16-bit error event to occur.

[0061] Referring now to FIG. 8 and FIG. 9, there is illustrated acomparison of the relative size and structure of the (16,11)concatenated C-TPC1 800 and the (64,57) concatenated C-TPC2 900. In FIG.8, there is an 11×11 array 802 of information bits, the row, column, andC/R parity bits, inclusively denoted as “Parity Bits” 804, andconcatenated parity bits 806 (that include both row parity bits, and C/Rparity bits). In FIG. 9, there is a 57×57 array 902 of information bits;the row, column, and C/R parity bits, inclusively denoted as “ParityBits” 904, and concatenated parity bits 906 (that include both rowparity bits, and C/R parity bits).

[0062] Referring not to FIG. 10 there is illustrated a graph 1000 of thesimulated performance curves for C-TPC2 900, and in comparison with theperformance curve 1002 of the “parent” (64,57)² TPC. Note that theperformance curve 1004 of C-TPC2 900 is the same, or slightly inferiorto that of the parent (64,57)² TPC 1002, when making a comparison in aregion above (or worse than) a BER of 10⁻⁵. However, for BERs that arebelow (better than) 10⁻⁵ (i.e., 10⁻⁶, 10⁻⁷, etc.) the performance curve1004 of C-TPC2 900 shows substantial improvement. Utilizing the (64,57)Extended Hamming code in a similar design, the code rate of the overallC-TPC (4544,3249) (C-TPC2) is 0.715. This represents a rate loss (withrespect to the (64,57)² TPC) of 0.45 dB. Thus the ACG for the(4544,3249) code would be better then the (4096,3249) code by 1.31 dB,wherein ACG=10log10(24*3249/4544)−10log10(16*2349/4096)=12.34−11.03=1.31dB.

[0063] This improvement comes about because the performance curve 1002of the parent TPC is performing at its asymptotic limit curve, and thusexhibits a flaring effect 1006 at the lower (or better) BERs.

[0064] Note that the performance curve 1002 of parent TPC was generatedutilizing sixty-four axis iterations. Three performance curves for theconcatenated C-TPC2 are provided: the performance curve 1004 derivedfrom sixty-four axis iterations ({fraction (5/16)} weight); aperformance curve 1008 derived from sixteen axis iterations ({fraction(5/16)} weight); and a performance curve 1010 derived from eight axisiterations ({fraction (5/16)} weight).

[0065] What is known is that at the last simulation data point (wherenine error events were logged), the number of bit errors per error eventis large (approximately sixty). Since the minimum distance is onlytwenty-four, the asymptotic performance has not been reached. Althoughthe performance at lower BERs is difficult to perform, if it is assumedthat the number of nearest neighbors for C-TPC2 is similar to the numberof nearest neighbors for the parent TPC (64,57)², then asymptoticperformance in the BER=10⁻¹² to 10⁻¹³ range corresponding to Eb/No≈3.5dB, can be reached.

[0066] Referring now to FIG. 1, there is illustrated a four-dimensionalcode 1100 embodiment achieved by adding an additional set of parity bits1102 to the C-TPC2 of FIG. 9. An improved code rate can be achieved byadding the additional set of parity bits 1102 to generate a (4983,3249)code, resulting in a code rate=0.657. A first of two versions of thiscode 1100 to be considered is a “random interleaver.” In this case, thelower right TPC 1104 (including both the 57×57 array of information bits1106 and the parity bits 1108) is constructed first. The array 1106 ofinformation bits (various bits denoted by 1107) is then copied to a new57×57 array 1110 of information bits in a pseudo random fashion using arandom interleaver 1112. This new information bit array 1110 is thenTPC-encoded from right to left, and bottom to top resulting in the upperleft TPC 1102. The original TPC 1104 and the parity bits 1114 from theupper left TPC 1102 are then transmitted.

[0067] Referring now to FIG. 12, there is illustrated a graph 1200 ofthe performance curve results for the code 1100 of FIG. 11. Theperformance curve 1002 for the parent (4096,3249) TPC was derived asbefore, with sixty-four axis iterations. A performance curve 1202represents the results for the concatenated code C-TPC3 when utilizing aflip-and-rotate interleaver with sixty-four axis iterations. Aperformance curve 1204 represents the results for the concatenated codeC-TPC3 when utilizing the random interleaver 1112 of FIG. 11 withsixty-four axis iterations. The C-TPC3 rate is approximately 0.657 andthe parent TPC rate is approximately 0.793.

[0068] In the second version of the C-TPC design, the information bitsare “scrambled” using the same “staggered diagonal rotation” interleaveras per C-TPC2. A graph 1300 of the simulated performance results isshown in FIG. 13. The performance curve 1002 for the parent (4096,3249)TPC was derived as before, with sixty-four axis iterations, and has acode rate of 0.793. The performance curve 1202 represents the resultsfor the concatenated code C-TPC3 when utilizing a flip-and-rotateinterleaver with sixty-four axis iterations, and has a code rate of0.657. Note that the performance of this variant of C-TPC3 is superiorto the performance utilizing the random interleaver 1112. However,neither code outperforms C-TPC2 (which has a higher code rate of 0.715).

[0069] Referring now to FIG. 14, there is illustrated the code C-TPC2900 of FIG. 9 where one additional a parity bit is added instead of themultiple parity bits 906. Thus the additional concatenated code 1401 isa parity code. This yields a (4160,3249) code 1400. Two variants forthis code 1400 are considered. In a first variant (C-TPC4), thefifty-seven leftmost columns of the parent (64,57)² are rotated (via the(63,57) Hamming code, only) in successive steps. For example, the firstleftmost column 1402 is not rotated (since it is not part of thecyclical Hamming code (63,57)), the second leftmost column 1404 isrotated one position, the third leftmost column 1406 is rotated twopositions, etc. By rotating only the fifty-seven leftmost columns, onlythe information bits and 6×57 (or 342 parity bits) partake in the“scrambling” operation. The fifty-seven leftmost bits per row (of whichthere are sixty-four rows) are then encoded with a (58,57) parity code.The resulting parity bits form the additional column 1401 that is a codeword from the (64,57) Extended Hamming code. This column 1401 ofsixty-four bits is then prepended to the left side of the array, asillustrated in FIG. 14.

[0070] For the second code variant (C-TPC5), which is not shown, therotation operation was extended to sixty-three columns, and the paritycode used is a (64,63) code. The 64^(th) column is purposely left out ofthe operation for the following reasons. First, rotating the finalcolumn one position more then the next-to-last column results in a fullsixty-three-position rotation that is not changed from its originalarrangement. (Recall that the last bit in an Extended Hamming code doesnot partake in the rotation operation since the Extended Hamming code isnot a cyclic code; only the sixty-three bits that make up the Hammingcode partake in the cyclic operation). Second, using a (k+1,k) code,where k is even, reduces the minimum distance of the concatenated code,since error locations associated with minimum-weight error events fromthe (64,57)² code can show up in even combinations when addresseddiagonally (which is essentially what the rotating operations aredoing). In this case, the (k+1,k) parity code will not “see” the errors.

[0071] Referring now to FIG. 15, there is illustrated a graph 1500 ofthe simulated performance curves for C-TPC4 and C-TPC5 utilizing variousweighting coefficients. The parent performance curve 1002 was derivedusing sixty-four axis iterations to arrive at a code rate ofapproximately 0.793. The performance curve 1502 for C-TPC4 was derivedusing sixty-four axis iterations to arrive at a code rate ofapproximately 0.781 (with a weight of {fraction (5/16)}). Theperformance curve 1504 for C-TPC4 was derived using sixty-four axisiterations to arrive at a code rate of approximately 0.781 (with aweight of {fraction (7/16)}). The performance curve 1506 for C-TPC5 wasderived using sixty-four axis iterations to arrive at a code rate ofapproximately 0.781 (with a weight of {fraction (5/16)}).

[0072] Note that the performance curves are very similar, and areslightly inferior to the performance of the parent code for BERs greaterthen 10⁻⁶, as indicated by the parent performance curve 1002. This isdue to the average error event for the parent code in this performancerealm exceeding the minimum distance of sixteen. The weaker parity codesimply cannot correct such corrupted blocks. As the parent code beginsto be dominated by minimum-weight error events, the parity code canidentify the occurrence of these error events and supply “correctingpower” for the iterative decoding process to lock in on the transmittedcode word.

[0073] Though C-TPC4 and C-TPC5 perform substantially identically, thenumber of iterations associated with C-TPC5 is, on average,significantly reduced with respect to the number of iterations requiredfor C-TPC4. For example, for Eb/No=3.3 dB, C-TPC4 requires fortyiterations (on average) while C-TPC5 requires less then ten. Thisrepresents a four-fold reduction in complexity for the C-TPC5. Thereason for the difference has to do with the way error events arecorrected between code iterations. The extra (concatenated) parity bits1401 associated C-TPC4 only cover the first fifty-seven columns. Becausethis covers all the information bits, it expands the minimum distance ofthe code from sixteen to twenty (as does C-TPC5). The parity bits fromthe (58,57) represent a relatively weak code. Upon completing SISOdecoding for the (58,57) code, the metrics are modified only minimally,and the right seven columns are not modified at all. As such, the effectof modifying the metrics via the (58,57) code takes several iterationsto “work through” to the seven rightmost columns. Only the singlerightmost column is left out of the decoding updates via the (64,63)parity encoding for C-TPC5. This results in the faster convergence.

[0074] The minimum distance of this code C-TPC4 is twenty, resulting inan increase in the ACG of 0.9 dB, with respect to the parent (64,57)²TPC code. This is a reduction in the ACG from the C-TPC2, where theimprovement in ACG is 1.31 dB. However the (4160,3249) code is of higherrate (rate=0.781). The C-TPC5 represents an excellent compromise betweenthe performance of the C-TPC2 and the simplicity of the parent (64,57)²TPC. It is estimated that the asymptotic performance of the code is notreached until BER≈10⁻¹¹, which represents quasi error-free performance.

[0075] Referring now to FIG. 16, there is illustrated a variation C-TPC81600 of the C-TPC5 code that is considered whereby both diagonals areprotected via parity codes. In this case, information bits 1602correspond to an inner (k+1,k)² TPC 1604, where k+1 is the number ofrows, and k is the number of columns. A single column 1606 of embeddedparity bits and a single row 1608 of embedded parity bits complete thisinner TPC 1604. In this particular example, the code 1600 includes onehundred twenty-one information bits that are obtained from a (121,100)TPC. The parity code words (rows and columns) need to fall on diagonals.To accomplish this, a (11,10)² TPC is first generated. A series ofrotations are then performed to ensure that row and column elements fallalong diagonals. An information bit array 1700 of FIG. 17 illustrates asimple indexing scheme of an 11×11 array representing the elements ofthe (11,10)² TPC. A “diagonal” array 1800 of FIG. 18 shows a diagonalmapping of the elements of the array 1700 of FIG. 17 such that row andcolumn elements fall along a first diagonal 1802 and a second diagonal1804, beginning the indexing at a center cell 1806 of the array 1800and, working downward and to the right.

[0076] The diagonal mapping of the inner TPC 1604 before encoding viathe outer TPC 1600 ensures that minimum-weight error events associatedwith the outer (256,121) TPC 1600 are easily identified via the inner(121,100) TPC 1604. This design increases the minimum distance of theoverall code from sixteen to twenty-four.

[0077] Referring now to FIG. 19, there is illustrated a graph 1900 ofsimulated performance curves associated with the code 1600 of FIG. 16.The performance curve 1002 of the parent (256,121) TPC is derivedutilizing sixty-four axis iterations. A performance curve 1902 of theC-TPC8 concatenated code is derived using thirty-two axis iterations.Note that the C-TPC8 code under-performs the parent (256,121)² TPC. Itis believed that there are a large number of neighbors for this code.The simulation results suggest that C-TPC8 will outperform its parentcode at BERs<10⁻⁸. However, this code design suffers 0.82 dB of rateloss due to the inner TPC 1604. This suggests that a C-TPC build with ahigher rate parent code might perform better.

[0078] A C-TPC9 code (not shown) is similar to the C-TPC8 code, but onlyconstructed with the (64,57)² TPC as the parent code. This code has ahigher rate (rate=0.766) and thus suffers less rate loss then the C-TPC8code. The simulated performance results are shown in FIG. 20. Theperformance curve 1002 of the parent (256,121) TPC is derived utilizingsixty-four axis iterations to achieve a rate of approximately 0.793. Aperformance curve 2002 of the C-TPC9 concatenated code is derived usinga weighting coefficient of {fraction (7/16)}.

[0079] The disclosed C-TPCs are can be implemented into a chip hardwarearchitecture, and require columns for the channel input array, the codedoutput array, and the difference areas. Additionally, mechanisms forreading data from, and writing data into the working arrays arerequired.

[0080] A number of the C-TPC designs have been simulated, and appear toperform better then their parent TPC code at low bit error rates. Twodesigns, the C-TPC2 and CTPC5, begin to show superior performance justas the code begins to exhibit asymptotic performance. This suggests thatthe disclosed C-TPC code is doing an excellent job of correcting theseerror events within the parent code. For codes that need to operate inthe quasi error-free performance regimes (BERs 10⁻¹⁰ to 10⁻¹⁴), theseC-TPCs represent some of the most powerful codes know with an elegantand efficient decoding method available with a demonstrated path to highperformance implementation.

[0081] Although the preferred embodiment has been described in detail,it should be understood that various changes, substitutions andalterations can be made therein without departing from the spirit andscope of the invention as defined by the appended claims.

What is claimed is:
 1. A method of encoding data of a data channel,comprising the steps of: arranging a stream of incoming information bitsinto a first array of information bits; processing the first array ofinformation bits into a first code of bits, which bits form a pluralityof first code words having a minimum distance to neighboring errorevents; rearranging selected bits of the first code into a second arrayof bits by intermittent successive rotations of the selected bits of thefirst code; and generating a second code from the second array of bitsto increase the minimum distance to the neighboring error events.
 2. Themethod of claim 1, wherein the first code in the step of processing is afirst turbo product code (TPC), and the second code in the step ofgenerating is a second TPC generated from the first TPC.
 3. The methodof claim 1, wherein the first array of information bits is processed bycolumn in the step of processing to derive column parity bits that areappended to the information bits, and wherein the first array ofinformation bits is processed by row in the step of processing to aderive row parity bits that are appended to the information bits.
 4. Themethod of claim 3, wherein each column of information bits is processedfrom top to bottom, and each row of information bits is processed fromleft to right.
 5. The method of claim 3, wherein columns of both theinformation bits and the column parity bits associated with a cyclicHamming code are rearranged in the step of rearranging.
 6. The method ofclaim 1, wherein columns of the information bits associated with acyclic Hamming code are rearranged in the step of rearranging.
 7. Themethod of claim 1, wherein the selected bits of the first code that arerearranged in the step of rearranging include columns that comprise bothinformation bits and column parity bits, and which selected bits ofcolumns forming a cyclic Hamming code are rotated successively accordingto a number of check bits of the Hamming code.
 8. The method of claim 1,wherein the number of neighboring error events is reduced by generatingthe second code in the step of generating.
 9. The method of claim 1,wherein the plurality of first code words are encoded by performing softinput-soft output turbo coding on the first array of information bits inthe step of processing.
 10. The method of claim 1, wherein the firstcode in the step of processing is an Extended Hamming code.
 11. Themethod of claim 1, wherein the second code is generated in the step ofgenerating by performing coding of the second array of information bitsand column parity bits generated in the step of processing, in aright-to-left manner to derive corresponding row parity bits.
 12. Themethod of claim 1, wherein a pseudo-random interleaver is utilized inthe step of rearranging to successively rotate columns of informationbits and associated column parity bits, which column parity bits aregenerated in the step of processing.
 13. The method of claim 1, whereinthe first code in the step of processing comprises an (n+1,k)² TPC ofExtended Hamming code words, which first code has n+1 columns thatinclude the information bits, such that the second array of bits isrearranged in the step of rearranging by rotating k-1 columns in asuccessively increasing manner with an extra rotation every (n-k)^(th)column.
 14. The method of claim 13, wherein all weight n+1 code wordsare eliminated by performing a double rotation every (n-k)^(th) column.15. The method of claim 1, wherein the first code and the second codeform a concatenated TPC having a code rate of at least 0.793.
 16. Themethod of claim 15, wherein the code rate is achieved utilizing at leastsixty-four axis iterations and a {fraction (5/16)} weightingcoefficient.
 17. A method of encoding data of a data channel, comprisingthe steps of: arranging a stream of incoming information bits into afirst array of information bits; processing the first array ofinformation bits into a first TPC of bits, which first TPC includes afirst set of column parity bits and a first set of row parity bits;rearranging the first array of information bits of the first code into asecond array of bits in a pseudo-random manner; generating a second setof column parity bits and a second set of row parity bits from thesecond array of bits; and transmitting the first TPC, the second set ofcolumn parity bits, and the second set of row parity bits.
 18. Themethod of claim 17, wherein the first TPC includes a first set of C/Rparity bits, and a second set of C/R parity bits are generated in thestep of generating such that both the first set of C/R parity bits andthe second set of C/R parity bits are transmitted in the step oftransmitting.
 19. A method of encoding data of a data channel,comprising the steps of: arranging a stream of incoming information bitsinto a first array of k-by-k information bits; processing the firstarray of information bits into a first code of bits, which first code ofbits form an (n+1,k)² TPC of Extended Hamming code words, and whichfirst code has k columns that include the information bits; rearrangingselected bits of the first code into a second array of bits by rotatingthe k columns of the first code in a successively increasing manner; andgenerating a second code from the second array of bits by encoding the kleftmost bits of each horizontal code word with a (k+1,k) parity codeword.
 20. The method of claim 19, wherein the k leftmost columns of bitsare rotated successively.
 21. A method of encoding data of a datachannel, comprising the steps of: arranging a stream of incominginformation bits into a first array of information bits; processing thefirst array of information bits into a first code of bits, which firstcode of bits form an (n+1,k)² TPC of Extended Hamming code words, andwhich first code has k columns that include the information bits;rearranging selected bits of the first code into a second array of bitsby rotating n columns of the first code in a successively increasingmanner; and generating a second code from the second array of bits byencoding the k leftmost bits of each horizontal code word with a (n+1,n)parity code word.
 22. The method of claim 21, wherein the k leftmostcolumns of bits are rotated successively in the step of arranging, andthe parity code word generated in the step of generating is prepended tothe first code.
 23. The method of claim 21, wherein the first code andthe second code form a concatenated TPC having a code rate of at least0.781.
 24. A method of encoding data of a data channel, comprising thesteps of: arranging a stream of incoming information bits into a firstarray of information bits; processing the first array of informationbits into a first code of bits, which first code of bits form a (k+1,k)²TPC of row elements and column elements; rearranging the first code intoa second array of bits such that the row elements and the columnelements fall along corresponding diagonals; and generating a secondcode by encoding the second array of bits.
 25. The method of claim 24,wherein the first code, which is a (64,57)² TPC, and the second codeform a concatenated TPC having a code rate of at least 0.766.
 26. Amethod of encoding information of a channel, comprising the steps of:providing a first code for processing the channel information;outputting processed information from said first code; providing asecond code which is generated from said first code by increasing theminimum distance of said first code; and processing said processedinformation with said second code to reduce the number of error eventswhich occur during processing of said first code, and to arrive at thecorrect channel information.
 27. An encoder for encoding information ofa channel, comprising: means for receiving a stream of incominginformation bits; means for arranging the stream of incoming informationbits into a first array of information bits; means for processing thefirst array of information bits into a first code of bits, which bitsform a plurality of first code words having a minimum distance toneighboring error events; means for rearranging selected bits of thefirst code into a second array of bits by intermittent successiverotations of the selected bits of the first code; and means forgenerating a second code from the second array of bits to increase theminimum distance to the neighboring error events.
 28. The encoder ofclaim 27, wherein the first code is a first turbo product code (TPC),and the second code is a second TPC generated from the first TPC. 29.The encoder of claim 27, wherein the first array of information bits isprocessed by column to derive column parity bits that are appended tothe information bits, and wherein the first array of information bits isprocessed by row to a derive row parity bits that are appended to theinformation bits.
 30. The encoder of claim 29, wherein each column ofinformation bits is processed from top to bottom, and each row ofinformation bits is processed from left to right.
 31. The encoder ofclaim 29, wherein columns of both the information bits and the columnparity bits associated with a cyclic Hamming code are rearranged. 32.The encoder of claim 27, wherein the selected bits of the first codethat are rearranged include columns that comprise both information bitsand column parity bits, and which selected bits of columns forming acyclic Hamming code are rotated successively according to a number ofcheck bits of the cyclic Hamming code.
 33. The encoder of claim 27,wherein the number of neighboring error events is reduced by generatingthe second code.
 34. The encoder of claim 27, wherein the plurality offirst code words are encoded by performing soft input-soft output turbocoding on the first array of information bits.
 35. The encoder of claim27, wherein the second code is generated by performing coding of thesecond array of information bits and column parity bits in aright-to-left manner to derive corresponding row parity bits.
 36. Theencoder of claim 27, wherein a pseudo-random interleaver is utilized tosuccessively rotate columns of information bits and associated columnparity bits, which column parity bits are generated.
 37. The encoder ofclaim 27, wherein the first code comprises an (n+1,k)² TPC of ExtendedHamming code words, which first code has n+1 columns that include theinformation bits, such that the second array of bits is rearranged byrotating k-1columns in a successively increasing manner with an extrarotation every (n-k)^(th) column.
 38. The encoder of claim 37, whereinall weight n+1 code words are eliminated by performing a double rotationevery (n-k)^(th) column.
 39. The encoder of claim 38, wherein the firstcode and the second code form a concatenated TPC having a code rate ofat least 0.793.
 40. The encoder of claim 39, wherein the code rate isachieved utilizing at least sixty-four axis iterations and a {fraction(5/16)} weighting coefficient.